Mentor Graphics ModelSim SE-64 10.7
ModelSim是经济高效的HDL模拟解决方案，集成了前所未有的验证能力。
除了支持标准HDL之外，ModelSim还提高了设计质量和调试效率。ModelSim屡获殊荣的单核模拟器（SKS）技术可以在一个设计中透明地混合VHDL和Verilog。它的体系结构允许独立于平台的编译，并具有本机编译代码的出色性能。
ModelSim packs an unprecedented level of verification capabilities in a cost-effective HDL simulation solution.
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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发布：CGer | 查看： | 发表时间：2019/5/27 14:20:31 | 更新时间：2019/5/27 14:31:00
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